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fedl610406-05 issue date: may. 23, 2014 ML610404/ml610405/ml610406 8-bit microcontroller with a built-in lcd driver 1/30 general description ML610404/ml610405/ml610406 is a high-performance 8-bit cmos microcontroller into which peripheral circuits, such as synchronous serial port, uart, melody driver, rc oscillation type a/d converter, and lcd driver, are incorporated around lapis semiconductor-original 8-bit cpu nx-u8/100. ML610404/ml610405/ml610406 operates in both high/low-speed mode and power-saving mode, it is most suitable for battery operated products. the short tat are entertained by offering mtp version ml610q407/ml610q408/ml610q409. ML610404p/ ml610405p/ml610406p support industrial temperature -40 c to +85 c, are added to the product lineup. features ? cpu ? 8-bit risc cpu (cpu name: nx-u8/100) ? instruction system: 16-bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? minimum instruction execution time 30.5 s (@32.768 khz system clock) 2 s (@500khz system clock) 0.5 s(@2mhz system clock) ? internal memory ? ML610404/5/6 : internal 8kbyte mask rom (4k 16 bits) (including unusable 128 byte test area) internal 256byte data ram (256 8 bits) ? interrupt controller ? 1 non-maskable interrupt sources internal source: 1 (watch dog timer) ? 27 maskable interrupt sources internal sources: 14 (synchronous serial port 0, synchronous serial port 1, timer0, timer1, timer2, timer3, uart0, melody0, rc oscillation type a/d converter, pwm0, tbc128hz, tbc32hz, tbc16hz, tbc2hz) external sources: 13 (p00, p01, p02, p03, p04, p50, p51, p52, p53, p54, p55, p56, p57) (one interrupt request is generated from p50 to p57 interrupt sources.) ? time base counter ? low-speed time base counter 1 channel frequency compensation (compensation range: approx. ? 488ppm to +488ppm. compensation accuracy: approx. 0.48ppm) ? high-speed time base counter 1 channel ? watchdog timer ? non-maskable interrupt and reset ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, 8s) ? timers ? 8 bits 4 channels [also available is 16-bit configuration (using timers 0 and 1, or timers 2 and 3) x 2 channels] ? clock frequency measurement function mode (16-bit configuration using timers 2 and 3 x 1 channel only)
fedl610406-05 ML610404/ml610405/ml610406 2/30 ? capture ? time base capture 2 channels (4096 hz to 32 hz) ? pwm ? resolution 16 bits 1 channel ? synchronous serial port ? master/slave selectable 2 channel ? lsb first/msb first selectable ? 8-bit length/16-bit length selectable ? uart ? txd/rxd 1 channel ? bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? built-in baud rate generator ? melody driver ? scale: 29 types (melody sound frequency: 508 hz to 32.768 khz) ? tone length: 63 types ? tempo: 15 types ? buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) ? rc oscillation type a/d converter ? 16-bit counter ? time division 2 channels ? general-purpose ports ? input-only port 5 channels (including secondary functions) ? output-only port ML610404: 12 channels (including secondary functions) ml610405: 8 channels (including secondary functions) ml610406: 4 channels (including secondary functions) ? input/output port 22 channels (including secondary functions) ? lcd driver number of segments ML610404: up to 105 dots (select among 21 segments x 5 commons, 22 segments x 4 commons, 23 segments x 3 commons, and 24segments x 2 commons) ml610405: up to 125 dots (select among 25 segments x 5 commons, 26 segments x 4 commons, 27 segments x 3 commons, and 28 segments x 2 commons) ml610406: up to 145 dots (select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments x 3 commons, and 32 segments x 2 commons) ? 1/1 to 1/5 duty ? 1/2, 1/3 bias (built-in bias generation circuit) ? frame frequency selecable: approx. 64hz, 73hz, 85hz, and 102hz ? bias voltage multiplying clock selectable (8 types) ? lcd drive stop mode, lcd display mode, all lcds on mode, and all lcds off mode selectable ? programmable display allocation function ? reset ? reset through the reset_n pin ? power-on reset generation when powered on ? reset when oscillation stop of the low-speed clock is detected (cancellation by a mask option is possible) ? reset by the watchdog timer (wdt) overflow
fedl610406-05 ML610404/ml610405/ml610406 3/30 ? clock ? low-speed clock (operation of this lsi is not guaranteed under a condition with no supply of low-speed crystal oscillation clock) crystal oscillation (32.768 khz) ? high-speed clock: built-in rc oscillation (500 khz, 2mhz) ? power management ? halt mode: suspends the instruction execution by cpu (peripheral circuits are in operating states) ? stop mode: stops the low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) ? high-speed clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) ? block control function: completely stops the operation of any function block circuit that is not used (resets registers and stops clock) ? guaranteed operating range ? operating temperature: -20c to +70c (p version: -40c to +85c) ? operating voltage: v dd = 1.25v to 3.6v
fedl610406-05 ML610404/ml610405/ml610406 4/30 ? product name ? supported function lcd bias - chip (die) - 1/2 1/3 low-speed oscillation stop detect reset operating temperature product availability ML610404- wa yes yes cancellation by a mask option is p ossible -20c to +70c yes ml610405- wa yes yes cancellation by a mask option is possible -20c to +70c yes ml610406- wa yes yes cancellation by a mask option is possible -20c to +70c yes ML610404p- wa yes yes cancellation by a mask option is possible -40c to +85c yes ml610405p- wa yes yes cancellation by a mask option is possible -40c to +85c yes ml610406p- wa yes yes cancellation by a mask option is possible -40c to +85c yes lcd bias -80-pin plastic tqfp - 1/2 1/3 low-speed oscillation stop detect reset operating temperature product availability ML610404- tb yes yes cancellation by a mask option is p ossible -20c to +70c - ml610405- tb yes yes cancellation by a mask option is possible -20c to +70c - ml610406- tb yes yes cancellation by a mask option is possible -20c to +70c - ML610404p- tb yes yes cancellation by a mask option is possible -40c to +85c - ml610405p- tb yes yes cancellation by a mask option is possible -40c to +85c ml610406p- tb yes yes cancellation by a mask option is possible -40c to +85c - xxx: rom code number (xxx of the blank product is nnn) q: mtp version p: wide range temperature version (p version) wa: chip (die) tb: tqfp
fedl610406-05 ML610404/ml610405/ml610406 5/30 block diagram block diagram of ML610404/ml610405/ml610406 * secondary function or tertiary function ?*1?: select among 21 segments x 5 commons, 22 segments x 4 commons, 23 segments x 3 commons, and 24 segments x 2 commons with the register ?*2?: select among 25 segments x 5 commons, 26 segments x 4 commons, 27 segments x 3 commons, and 28 segments x 2 commons with the register ?*3?: select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments x 3 commons, and 32 segments x 2 commons with the register figure 1 block diagram of ML610404/ml610405/ml610406 program memory (rom) 8kbyte ram 256byte interrupt controller cpu (nx-u8/100) timing controller ea sp instruction decoder bus controller instruction register tbc int 4 int 1 wdt int 8bit timer 4 capture 2 gpio int 6 data-bus melody int 1 md0* test0 reset_n osc xt0** xt1** lsclk* outclk* power v ddl lcd driver com0 to com4 (*1)(*2)(*3) seg0 to seg23 (ML610404) (*1) seg0 to seg27 (ml610405) (*2) seg0 to seg31 ( ml610406 ) (*3) lcd bias v l1 , v l2 , v l3 c1 , c2 rc-adc 2 cs0* in0* rs0* rt0* rct0* rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v dd v ss int 1 display register 320bit display allocation ram p00 to p04 p20 to p23, p24 p30 to p35 p40 to p47 p50 to p57 p60 to p67 (ML610404) p60 to p63 (ml610405) ssio 2 sck0* sin0* sout0* int 2 sck1* sin1* sout1* uart rxd0* txd0* int 1 int 1 pwm pwm0*
fedl610406-05 ML610404/ml610405/ml610406 6/30 pin configuration pin layout of ML610404 chip note: the assignment of the pads p30 to p35 are not in order. chip size: 2.1 mm 2.1 mm pad count: 78 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss leve figure 2 dimensions of ML610404 chip 29 28 27 26 p53 p54 p55 p56 p57 p35 p33 p32 p34 p31 71 p30 70 p04 69 p03 68 p02 67 p01 66 p00 65 p24 64 63 78 77 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 c2 c1 p60 p61 p62 p63 p64 p65 p66 p67 seg23 seg22 seg21 seg20 seg19 seg18 32 31 30 35 34 33 38 37 36 21 20 39 22 53 54 55 56 57 58 59 51 52 12 1 2 3 4 5 6 7 8 9 11 10 13 14 15 p50 p40 p41 p42 p43 p44 p45 p46 p47 v dd v ss v ddl xt0 xt1 reset_n test0 v l1 v l2 v l3 16 17 18 19 25 24 23 47 48 49 50 45 46 73 72 75 74 y x 2.1 mm 2.1 mm 76 seg17 seg16 43 44 41 42 40 p22 p21 p20 v ss p52 p51 62 61 60
fedl610406-05 ML610404/ml610405/ml610406 7/30 pin layout of ml610405 chip note: the assignment of the pads p30 to p35 are not in order. chip size: 2.1 mm 2.1 mm pad count: 78 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 3 dimensions of ml610405 chip 29 28 27 26 p53 p54 p55 p56 p57 p35 p33 p32 p34 p31 71 p30 70 p04 69 p03 68 p02 67 p01 66 p00 65 p24 64 63 78 77 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 c2 c1 p60 p61 p62 p63 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 32 31 30 35 34 33 38 37 36 21 20 39 22 53 54 55 56 57 58 59 51 52 12 1 2 3 4 5 6 7 8 9 11 10 13 14 15 p50 p40 p41 p42 p43 p44 p45 p46 p47 v dd v ss v ddl xt0 xt1 reset_n test0 v l1 v l2 v l3 16 17 18 19 25 24 23 47 48 49 50 45 46 73 72 75 74 y x 2.1 mm 2.1 mm 76 seg17 seg16 43 44 41 42 40 p22 p21 p20 v ss p52 p51 62 61 60
fedl610406-05 ML610404/ml610405/ml610406 8/30 pin layout of ml610406 chip note: the assignment of the pads p30 to p35 are not in order. chip size: 2.1 mm 2.1 mm pad count: 78pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 4 dimensions of ml610406 chip 29 28 27 26 p53 p54 p55 p56 p57 p35 p33 p32 p34 p31 71 p30 70 p04 69 p03 68 p02 67 p01 66 p00 65 p24 64 63 78 77 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 c2 c1 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 32 31 30 35 34 33 38 37 36 21 20 39 22 53 54 55 56 57 58 59 51 52 12 1 2 3 4 5 6 7 8 9 11 10 13 14 15 p50 p40 p41 p42 p43 p44 p45 p46 p47 v dd v ss v ddl xt0 xt1 reset_n test0 v l1 v l2 v l3 16 17 18 19 25 24 23 47 48 49 50 45 46 73 72 75 74 y x 2.1 mm 2.1 mm 76 seg17 seg16 43 44 41 42 40 p22 p21 p20 v ss p52 p51 62 61 60
fedl610406-05 ML610404/ml610405/ml610406 9/30 pad coordinates of ML610404/ml610405/m610406 chip table 1 pad coordinates of ML610404/ml610405/ml610406 chip center: x=0,y=0 ML610404/5/6 ML610404/5/6 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 1 p50 -773 -944 44 seg20 450 944 2 p40 -693 -944 45 seg21 370 944 3 p41 -613 -944 46 seg22 290 944 4 p42 -533 -944 47 seg23 210 944 5 p43 -453 -944 p67 (*1) 6 p44 -373 -944 48 seg24 (*2)(*3) 115 944 7 p45 -293 -944 p66 (*1) 8 p46 -213 -944 49 seg25 (*2)(*3) 35 944 9 p47 -133 -944 p65 (*1) 10 v dd -53 -944 50 seg26 (*2)(*3) -45 944 11 v ss 27 -944 p64 (*1) 12 v ddl 107 -944 51 seg27 (*2)(*3) -125 944 13 xt0 187 -944 p63 (*1)(*2) 14 xt1 347 -944 52 seg28 (*3) -205 944 15 reset_n 427 -944 p62 (*1)(*2) 16 test0 507 -944 53 seg29 (*3) -285 944 17 v l1 587 -944 p61 (*1)(*2) 18 v l2 667 -944 54 seg30 (*3) -365 944 19 v l3 747 -944 p60 (*1)(*2) 20 c1 944 -810 55 seg31 (*3) -445 944 21 c2 944 -730 56 v ss -525 944 22 com0 944 -650 57 p20 -605 944 23 com1 944 -570 58 p21 -685 944 24 com2/seg0 944 -490 59 p22 -765 944 25 com3/seg1 944 -410 60 p24 -944 717 26 com4/seg2 944 -330 61 p00 -944 617 27 seg3 944 -250 62 p01 -944 537 28 seg4 944 -170 63 p02 -944 457 29 seg5 944 -90 64 p03 -944 377 30 seg6 944 -10 65 p04 -944 297 31 seg7 944 70 66 p30 -944 217 32 seg8 944 150 67 p31 -944 137 33 seg9 944 230 68 p34 -944 57 34 seg10 944 310 69 p32 -944 -23 35 seg11 944 390 70 p33 -944 -103 36 seg12 944 470 71 p35 -944 -183 37 seg13 944 550 72 p57 -944 -263 38 seg14 944 630 73 p56 -944 -343 39 seg15 944 710 74 p55 -944 -423 40 seg16 770 944 75 p54 -944 -503 41 seg17 690 944 76 p53 -944 -583 42 seg18 610 944 77 p52 -944 -663 43 seg19 530 944 78 p51 -944 -743 (*1) pad for ML610404 . (*2) pad for ml610405. (*3) pad for ml610406
fedl610406-05 ML610404/ml610405/ml610406 10/30 list of pins primary function secondary function or tertiary function pin no. pad no. pin name i/o function secondary/ tertiary pin name i/o function 11,57 11,56 vss ? negative power supply pin ? ? ? ? 10 10 v dd ? positive power supply pin ? ? ? ? 12 12 v ddl ? power supply pin for internal logic (internally generated) ? ? ? ? 18 17 v l1 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*1) ? ? ? ? 19 18 v l2 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*1) ? ? ? ? 20 19 v l3 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*1) ? ? ? ? 21 20 c1 ? capacitor connection pin for lcd bias generation ? ? ? ? 22 21 c2 ? capacitor connection pin for lcd bias generation ? ? ? ? 17 16 test0 i/o test input pin ? ? ? ? 16 15 reset_n i reset input pin ? ? ? ? 14 13 xt0 i low-speed clock oscillation pin ? ? ? ? 15 14 xt1 o low-speed clock oscillation pin ? ? ? ? 62 61 p00/exi0/ cap0 i input port, external interrupt, capture 0 input ? ? ? ? 63 62 p01/exi1/ cap1 i input port, external interrupt, capture 1 input ? ? ? ? 64 63 p02/exi2/ rxd0 i input port, external interrupt, uart0 received data ? ? ? ? 65 64 p03/exi3 i input port, external interrupt ? ? ? ? 66 65 p04/exi4/ t02p0ck i input port, timer 0/timer 2/pwm0 external clock input external interrupt ? ? ? ? 58 57 p20/led0 o output port secondary lsclk o low-speed clock output 59 58 p21/led1 o output port secondary outclk o high-speed clock output 60 59 p22/led2 o output port secondary md0 o melody 0 output 61 60 p24/led4 o output port secondary pwm0 o pwm0 output 67 66 p30 i/o input/output port secondary in0 i rc type adc0 oscillation input pin 68 67 p31 i/o input/output port secondary cs0 o rc type adc0 reference capacitor connection pin 69 68 p34 i/o input/output port secondary rct0 o rc type adc0 resistor/capacitor sensor connection pin 70 69 p32 i/o input/output port secondary rs0 o rc type adc0 reference resistor connection pin 71 70 p33 i/o input/output port secondary rt0 o rc type adc0 measurement resistor sensor connection pin 72 71 p35 i/o input/output port secondary rcm o rc type adc oscillation monitor
fedl610406-05 ML610404/ml610405/ml610406 11/30 primary function secondary function or tertiary function pin no. pad no. pin name i/o function secondary /tertiary pin name i/o function secondary ? ? ? 2 2 p40 i/o input/output port tertiary sin0 i ssio0 data input secondary ? ? ? 3 3 p41 i/o input/output port tertiary sck0 i/o ssio0 synchronous clock input/output secondary rxd0 i uart data input 4 4 p42 i/o input/output port tertiary sout0 o ssio0 data output secondary txd0 o uart data output 5 5 p43 i/o input/output port tertiary pwm0 o pwm0 output secondary in1 i rc type adc1 oscillation input pin 6 6 p44/ t02p0ck i/o input/output port, timer 0/timer 2/pwm0 external clock input tertiary sin0 i ssio0 data input secondary cs1 o rc type adc1 reference capacitor connection pin 7 7 p45/t13ck i/o input/output port, timer 1/timer 3 external clock input tertiary sck0 i/o ssio0 synchronous clock input/output secondary rs1 o rc type adc1 reference resistor connection pin 8 8 p46 i/o input/output port tertiary sout0 o ssio0 data output 9 9 p47 i/o input/output port secondary rt1 o rc type adc1 measurement resistor sensor connection pin secondary md0 o melody 0 output 1 1 p50/exi8 i/o input/output port, external interrupt tertiary sin1 i ssio1 data input secondary ? ? ? 79 78 p51/exi8 i/o input/output port, external interrupt tertiary sck1 i/o ssio1 synchronous clock input/output secondary ? ? ? 78 77 p52/exi8 i/o input/output port, external interrupt tertiary sout1 o ssio1 data output 77 76 p53/exi8 i/o input/output port, external interrupt ? ? ? ? secondary ? ? ? 76 75 p54/exi8 i/o input/output port, external interrupt tertiary sin1 i ssio1 data input secondary ? ? ? 75 74 p55/exi8 i/o input/output port, external interrupt tertiary sck1 i/o ssio1 synchronous clock input/output secondary ? ? ? 74 73 p56/exi8 i/o input/output port, external interrupt tertiary sout1 o ssio1 data output 73 72 p57/exi8 i/o input/output port, external interrupt ? ? ? ?
fedl610406-05 ML610404/ml610405/ml610406 12/30 primary function secondary function or tertiary function pin no. pad no. pin name i/o function secondary/ tertiary pin name i/o function 23 22 com0 o lcd common pin ? ? ? ? 24 23 com1 o lcd common pin ? ? ? ? 25 24 com2/ seg0 o lcd common/segment pin ? ? ? ? 26 25 com3/ seg1 o lcd common/segment pin ? ? ? ? 27 26 com4/ seg2 o lcd common/segment pin ? ? ? ? 28 27 seg3 o lcd segment pin ? ? ? ? 29 28 seg4 o lcd segment pin ? ? ? ? 30 29 seg5 o lcd segment pin ? ? ? ? 31 30 seg6 o lcd segment pin ? ? ? ? 32 31 seg7 o lcd segment pin ? ? ? ? 33 32 seg8 o lcd segment pin ? ? ? ? 34 33 seg9 o lcd segment pin ? ? ? ? 35 34 seg10 o lcd segment pin ? ? ? ? 36 35 seg11 o lcd segment pin ? ? ? ? 37 36 seg12 o lcd segment pin ? ? ? ? 38 37 seg13 o lcd segment pin ? ? ? ? 39 38 seg14 o lcd segment pin ? ? ? ? 40 39 seg15 o lcd segment pin ? ? ? ? 41 40 seg16 o lcd segment pin ? ? ? ? 42 41 seg17 o lcd segment pin ? ? ? ? 43 42 seg18 o lcd segment pin ? ? ? ? 44 43 seg19 o lcd segment pin ? ? ? ? 45 44 seg20 o lcd segment pin ? ? ? ? 46 45 seg21 o lcd segment pin ? ? ? ? 47 46 seg22 o lcd segment pin ? ? ? ? 48 47 seg23 o lcd segment pin ? ? ? ? p67 (*2) o output port ? ? ? ? 49 48 seg24 (*3) o lcd segment pin ? ? ? ? p66 (*2) o output port ? ? ? ? 50 49 seg25 (*3) o lcd segment pin ? ? ? ? p65 (*2) o output port ? ? ? ? 51 50 seg26 (*3) o lcd segment pin ? ? ? ? p64 (*2) o output port ? ? ? ? 52 51 seg27 (*3) o lcd segment pin ? ? ? ? p63 (*4) o output port ? ? ? ? 53 52 seg28 (*5) o lcd segment pin ? ? ? ? p62 (*4) o output port ? ? ? ? 54 53 seg29 *5) o lcd segment pin ? ? ? ? p61 (*4) o output port ? ? ? ? 55 54 seg30 (*5) o lcd segment pin ? ? ? ? p60 (*4) o output port ? ? ? ? 56 55 seg31 (*5) o lcd segment pin ? ? ? ? (* 1 ) internally generated, or connect to either positive power supply pin (v dd ) or power supply pin for internal logic (v ddl ). for details, see user?s manual. (* 2 ) pin for ML610404 (* 3 ) pin for ml610405/ml610406 (* 4 ) pin for ML610404/ml610405 (* 5 ) pin for ml610406
fedl610406-05 ML610404/ml610405/ml610406 13/30 pin description pin name i/o description primary/ secondary/ tertiary logic system reset_n i reset input pin. when this pin is set to a ?l? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, program execution starts. a pull-up resistor is internally connected. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal resonator is connected to this pin. capacitors c dl and c gl are connected across this pin and v ss . (see measuring circuit 1) . ? ? lsclk o low-speed clock output. assigned to the secondary function of the p20 pin. secondary ? outclk o high-speed clock output pin. this pin is used as the secondary function of the p21 pin. secondary ? general-purpose input port p00 to p04 i general-purpose input port. primary positive general-purpose output port p20 to p22, p24 o general-purpose output port. this cannot be used as the general output port when used as the secondary function. primary positive general-purpose input/output port p30 to p35 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary function. primary positive p40 to p47 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary or tertiary function. primary positive p50 to p57 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary function. primary positive p60 to p63 o general-purpose output port. incorporated only into ML610404/ml610405, and not into ml610406. primary positive p64 to p67 o general-purpose output port. incorporated only into ML610404, and not into ml610405/ ml610406. primary positive
fedl610406-05 ML610404/ml610405/ml610406 14/30 pin name i/o description primary/ secondary/ tertiary logic uart txd0 o uart data output pin. this pin is used as the secondary function of the p43 pin. secondary positive rxd0 i uart data input pin. this pin is used as the secondary function of the p42 or the primary function of the p02 pin. primary/ secondary positive synchronous serial (ssio) sck0 i/o synchronous serial clock input/output pin. this pin is used as the tertiary function of the p41 or p45 pin. tertiary ? sin0 i synchronous serial data input pin. this pin is used as the tertiary function of the p40 or p44 pin. tertiary positive sout0 o synchronous serial data output pin. this pin is used as the tertiary function of the p42 or p46 pin. tertiary positive sck1 i/o synchronous serial clock input/output pin. assigned to the tertiary function of the p51 pin and p55 pin. tertiary ? sin1 i synchronous serial data input pin. assigned to the tertiary function of the p50 pin and p54 pin. tertiary positive sout1 o synchronous serial data output pin. assigned to the tertiary function of the p52 pin and p56 pin. tertiary positive pwm pwm0 o pwm0 output pin. this pin is used as the secondary function of the p24 and tertiary function of the p43 pin. secondary tertiary positive t02p0ck o pwm0 external clock input pin. this pin is used as the primary function of the p04 pin and p44 pin. primary ? external interrupt exi0-4 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p00 to p04 pins. primary positive/ negative exi8 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. assigned to the primary function of the p50 to p57 pins. primary positive/ negative capture cap0 i primary positive/ negative cap1 i capture trigger input pins. the value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. these pins are used as the primary functions of the p00 pin(cap0) and p01 pin(cap1). primary positive/ negative timer t02p0ck i external clock input pin used for both timer 0 and timer 2. this pin is used as the primary function of the p04 pin and p44 pin. primary ? t13ck i external clock input pin used for both timer 1 and timer 3. this pin is used as the primary function of the p45 pin. primary ? melody md0 o melody/buzzer signal output pin. this pin is used as the secondary function of the p22 and p50 pins. secondary positive/ negative led drive led0 to led2, led4 o n-channel open drain output pins to drive led. this pin is used as the primary function of the p20 to p22 and p24 pins. primary positive/ negative
fedl610406-05 ML610404/ml610405/ml610406 15/30 pin name i/o description primary/ secondary/ tertiary logic rc oscillation type a/d converter in0 i channel 0 oscillation input pin. this pin is used as the secondary function of the p30 pin. secondary ? cs0 o channel 0 reference capacitor connection pin. this pin is used as the secondary function of the p31 pin. secondary ? rs0 o this pin is used as the secondary function of the p32 pin which is the reference resistor connection pin of channel 0. secondary ? rct0 o resistor/capacitor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p34 pin. secondary ? rt0 o resistor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p33 pin. secondary ? rcm o rc oscillation monitor pin. this pin is used as the secondary function of the p35 pin. secondary ? in1 i oscillation input pin of channel 1. this pin is used as the secondary function of the p44 pin. secondary ? cs1 o reference capacitor connection pin of channel 1. this pin is used as the secondary function of the p45 pin. secondary ? rs1 o reference resistor connection pin of channel 1. this pin is used as the secondary function of the p46 pin. secondary ? rt1 o resistor sensor connection pin for measurement of channel 1. this pin is used as the secondary function of the p47 pin. secondary ? lcd drive signal com0 to com4 o common output pins. com2, com3, and com4 can be switched to seg0, seg1, and seg2, respectively, through the register setting. to change the setting, switch between com4 and seg2 for one pin and switch between com3, com4 and seg1, seg2 for two pins. ? ? seg0 to seg23 o segment output pin. the seg0, seg1, and seg2 pins are for switching the register setting with the com2, com3, and com4. ? ? seg24 to seg27 o segment output pin. incorporated into ml610405/ml610406, not into ML610404. ? ? seg28 to seg31 o segment output pin. incorporated into ml610406, not into ML610404/ml610405. ? ? lcd driver power supply v l1 ? ? ? v l2 ? ? ? v l3 ? power supply pin for lcd bias (internally generated) or power supply connection pin. depending on lcd bias setting and v dd voltage level, v dd or v ddl or capacitor is connected. ? ? c1 ? ? ? c2 ? power supply pins for lcd bias (internally generated). capacitor c 12 (see measuring circuit 1) is connected between c1 and c2. ? ? for testing test0 i/o pin for testing. a pull-down resistor is internally connected. ? positive power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin. ? ? v ddl ? positive power supply pin (internally generated) for internal logic. capacitor c l (see measuring circuit 1) is connected between this pin and v ss . ? ?
fedl610406-05 ML610404/ml610405/ml610406 16/30 termination of unused pins table 3 shows methods of terminating the unused pins. table 3 termination of unused pins pin recommended pin handling vl1 open vl2 open vl3 open c1, c2 open reset_n open test0 open p00 to p04 vdd or vss p20 to p22, p24 open p30 to p35 open p40 to p47 open p50 to p57 open p60 to p67 open com0 to com4 open seg0 to seg31 open note: it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.
fedl610406-05 ML610404/ml610405/ml610406 17/30 electrical characteristics absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta = 25 c ? 0.3 to +4.6 v power supply voltage 2 v ddl ta = 25 c ? 0.3 to +3.6 v power supply voltage 3 v l1 ta = 25 c ? 0.3 to +2.0 v power supply voltage 4 v l2 ta = 25 c ? 0.3 to +4.0 v power supply voltage 5 v l3 ta = 25 c ? 0.3 to +6.0 v input voltage v in ta = 25 c ? 0.3 to v dd +0.3 v output voltage v out ta = 25 c ? 0.3 to v dd +0.3 v output current 1 i out1 port 3 to 6, ta = 25 c ? 12 to +11 ma output current 2 i out2 port 2, ta = 25 c ? 12 to +20 ma power dissipation pd ta = 25 c 0.9 w storage temperature t stg ? ? 55 to +150 c recommended operating conditions (v ss = 0v) parameter symbol condition range unit without p version -20 to +70 operating temperature t op p version -40 to +85 c f op = 30k to 625khz 1.25 to 3.6 operating voltage v dd f op = 30k to 2.5mhz 1.8 to 3.6 v v dd = 1.25 to 3.6v 30k to 625k operating frequency (cpu) f op v dd = 1.8 to 3.6v 30k to 2.5m hz v dd pin external capacitance c v D 1.030% to 2.230%* 1 f v ddl pin external capacitance c l ? 0.4730% to 2.230%* 2 f v l1, 2, or 3 pin external capacitance c a, b, c ? 0.1 30% f pin-to-pin (c1 to c2) external capacitance c 12 ? 0.47 30% f * 1 : please select as c v is larger than c l or same as c l . * 2 : when the load of vdd is small and the power rise time is too short, it may happen that the power-on reset is not generated. in this case please select c l with larger capacitance clock generation circuit operating conditions (v ss = 0v) rating parameter symbol condition min. typ. max. unit low-speed crystal oscillation frequency f xtl ? ? 32.768k ? hz recommended equivalent series resistance value of low-speed crystal oscillation r l ? ? ? 40k ? c l =6pf of crystal oscillation ? 12 ? c l =9pf of crystal oscillation ? 18 ? low-speed crystal oscillation external capacitor c dl /c gl c l =12pf of crystal oscillation ? 24 ? pf
fedl610406-05 ML610404/ml610405/ml610406 18/30 dc characteristics (1/5) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ta = 25 c typ. ? 10% 500 typ. + 10% v dd = 1.25 to 3.6v * 3 typ. ? 25% 500 typ. + 25% khz ta = 25 c typ. ? 10% 2.0 typ. + 10% 500khz/2mhz rc oscillation frequency f rc v dd = 1.80 to 3.6v * 3 typ. ? 25% 2.0 typ. + 25% mhz low-speed crystal oscillation start time* 2 t xtl ? ? 0.6 2 s 500khz/2mhz rc oscillation start time t rc ? ? ? 3 s low-speed oscillation stop detect time *1 t stop ? 12 16.4 41 ms reset pulse width p rst ? 200 ? ? reset noise elimination pulse width p nrst ? ? ? 0.3 s power-on reset generated power rise time t por ? ? ? 10 ms 1 * 1 : when low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. * 2 : 32.768khz crystal resonator dt-26 (load capacitanc e 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =6pf) * 3 : recommended operating temperature (ta=-20 to 70 c, ta=-40 to 85 c for p version) reset_n reset pulse width (p rst ) vdd 0.9xv dd 0.1xv dd t por powe r -on reset activation power rise time (t por ) p rst vil1 vil1
fedl610406-05 ML610404/ml610405/ml610406 19/30 dc characteristics (2/5) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit f op = 30k to 625khz 1.1 1.2 1.3 v ddl voltage v ddl f op = 30k to 2.5mhz 1.35 1.5 1.65 v v ddl temperature deviation * 1 ? v ddl v dd = 3.0v ? -1 ? mv/ c v ddl voltage dependency * 1 ? v ddl ? ? 5 20 mv/v 1 * 1 : the maximum v ddl voltage becomes the v dd voltage level when the v ddl voltage determined by the temperature and voltage deviations mathematically exceeds the v dd voltage.
fedl610406-05 ML610404/ml610405/ml610406 20/30 dc characteristics (3/5) (v dd =3.0v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ta= 25 c ? 0.4 0.8 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped. * 5 ? ? 6.5 a ta= 25 c ? 0.9 1.8 supply current 2 idd2 cpu: in halt state (ltbc and wdt are operating.).* 3 * 4 high-speed 500khz/2mhz oscillation: stopped. lcd and bias circuits: operating. * 6 * 5 ? ? 7.5 a ta= 25 c ? 4.0 7.5 supply current 3 idd3 cpu: in 32.768khz operating state.* 1 * 3 high-speed 500khz/2mhz oscillation: stopped. lcd and bias circuits: operating. * 2 * 5 ? ? 11.0 a 1 ta= 25 c ? 60 80 supply current 4-1 idd4-1 cpu: in 500khz rc operating state. lcd/bias circuits: operating. * 2 * 5 ? ? 90 a ta= 25 c ? 240 300 supply current 4-2 idd4-2 cpu: in 2mhz rc operating state. lcd/bias circuits: operating. * 2 * 5 ? ? 320 a 1 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : all segs: off waveform, no lcd panel load, 1/3 bias, 1/3 duty, frame frequency: approx. 64 hz, bias voltage multiplying clock: 1/128 lsclk (256hz) * 3 : 32.768khz crystal resonator dt-26 (load capacitanc e 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =6pf). * 4 : significant bits of blkcon0 to blkcon4 registers are all ?1? except dlcd bit on blkcon4. * 5 : recommended operating temperature (ta=-20 to 70 c, ta=-40 to 85 c for p version) * 6 : lcd stop mode, 1/3 bias, bias voltage multiplying clock: 1/128 lsclk (256hz)
fedl610406-05 ML610404/ml610405/ml610406 21/30 dc characteristics (4/5) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ioh1 = ? 0.5ma, v dd = 1.8 to 3.6v v dd ? 0.5 ? ? voh1 ioh1 = -0.03ma, v dd = 1.25 to 3.6v v dd ? 0.3 ? ? iol1 = +0.5ma, v dd = 1.8 to 3.6v ? ? 0.5 output voltage 1 (p20 to p22,p24 (n-channel open drain output mode is not selected)) (p30 to p35) (p40 to p47) (p50 to p57) (p60 to p63) *2 (p60 to p67) *1 vol1 iol1 = +0.1ma, v dd = 1.25 to 3.6v ? ? 0.3 output voltage 2 (p20 to p22,p24 (n-channel open drain output mode is not selected)) vol2 iol2 = +5ma, v dd = 1.8 to 3.6v ? ? 0.5 voh3 ioh3 = ? 0.05ma, vl1=1.2v v l3 ? 0.2 ? ? voml3 ioml3 = +0.05ma, vl1=1.2v ? ? v l2 +0.2 voml3s ioml3s = ? 0.05ma, vl1=1.2v v l2 ?0.2 ? ? volm3 iolm3 = +0.05ma, vl1=1.2v ? ? v l1 +0.2 volm3s iolm3s = ? 0.05ma, vl1=1.2v v l1 ? 0.2 ? ? output voltage 3 (com0 to 4) (seg0 to 23) *1 (seg0 to 27) *2 (seg0 to 31) *3 vol3 iol3 = +0.05ma, vl1=1.2v ? ? 0.2 v 2 iooh voh = v dd (in high-impedance state) ? ? 1 output leakage (p20 to p22,p24) (p30 to p35) (p40 to p47) (p50 to p57) (p60 to p63) *2 (p60 to p67) *1 iool vol = v ss (in high-impedance state) ? 1 ? ? a 3 iih1 vih1 = v dd ? ? 1 input current 1 (reset_n) iil1 vil1 = v ss -600 -300 -2 iih2 vih2 = v dd 2 300 600 input current 2 (test0) iil2 vil2 = v ss -1 ? ? vih3 = v dd, v dd = 1.8 to 3.6v (when pulled-down) 2 30 200 iih3 vih3 = v dd, v dd = 1.25 to 3.6v (when pulled-down) 0.01 30 200 vil3 = v ss, v dd = 1.8 to 3.6v (when pulled-up) -200 -30 -2 iil3 vil3 = v ss, v dd = 1.25 to 3.6v (when pulled-up) -200 -30 -0.01 iih3z vih3 = v dd (in high-impedance state) ? ? 1 input current 3 (p00 to p04) (p30 to p35) (p40 to p47) (p50 to p57) iil3z vil3 = v ss (in high-impedance state) ? 1 ? ? a 4 * 1 : characteristics for ML610404 * 2 : characteristics for ml610405 * 3 : characteristics for ml610406
fedl610406-05 ML610404/ml610405/ml610406 22/30 dc characteristics (5/5) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit vih1 ? 0.7 v dd ? v dd v dd = 1.8 to 3.6v 0 ? 0.3 v dd input voltage 1 (reset_n) (test0) (p00 to p04) (p30 to p35) (p40 to p47) (p50 to p57) vil1 v dd = 1.25 to 3.6v 0 ? 0.2 v dd v 5 input pin capacitance (p00 to p04) (p30 to p35) (p40 to p47) (p50 to p57) cin f = 10khz v rms = 50mv ta = 25 c ? ? 5 pf ?
fedl610406-05 ML610404/ml610405/ml610406 23/30 measuring circuits measuring circuit 2 input pin v v dd v ddl v l1 v l2 v l3 v ss vih vil output pin (note 1) input logic circuit to determine the specified measuring conditions. (note 2) repeats for the specified output pin (note 2) (note 1) xt0 xt1 a v dd v ddl c l v l1 c a v l2 v l3 c c v ss c2 c1 c 12 c v : 1f c l : 2.2uf c a ,c b ,c c : 0.1f c 12 : 0.47f 32.768khz crystal resonator : dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) c gl , c dl : 6pf c v c dl 32.768khz crystal resonator c gl
fedl610406-05 ML610404/ml610405/ml610406 24/30 measuring circuit 3 measuring circuit 4 measuring circuit 5 input pin v dd v ddl v l1 v l2 v l3 v ss vih vil output pin (note 1) input logic circuit to determine the specified measuring conditions. (note 1) waveform observation input pin a v dd v ddl v l1 v l2 v l3 v ss output pin (note 3) repeats for the specified input pin (note 3) input pin a v dd v ddl v l1 v l2 v l3 v ss vih vil output pin (note 1) input logic circuit to determine the specified measuring conditions. (note 2) repeats for the specified output pin (note 2) (note 1)
fedl610406-05 ML610404/ml610405/ml610406 25/30 ac characteristics (external interrupt) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation system clock: 32.768khz 76.8 ? 106.8 s ac characteristics (uart) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit transmit baud rate t tbrt ? ? brt* 1 ? s receive baud rate t rbrt ? brt* 1 ? 3% brt* 1 brt* 1 +3% s *1: baud rate period (including the error of the clock frequency selected) set with the uart baud rate register ( ua0brtl,h ) and the uart mode register 0 ( ua0mod0 ). t nul p00 to p04 (rising-edge interrupt mode) p00 to p04 (falling-edge interrupt mode) p00 to p04 p50 to p57 (both-edge interrupt mode) t nul t nul t rbrt txd0* rxd0* *: indicates the secondary function of the port. t tbrt
fedl610406-05 ML610404/ml610405/ml610406 26/30 ac characteristics (synchronous serial port) (v dd = 1.25 to 3.6v, v ss =0v, ta= -20 to +70c, ta= -40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit in the 500khz oscillation mode* 2 10 D D s sclk input cycle (slave mode) t scyc in the 2mhz oscillation mode* 3 v dd =1.8 to 3.6v 1 D D s sclk output cycle (master mode) t scyc D D sclk* 1 D s in the 500khz oscillation mode* 2 4 D D s sclk input pulse width (slave mode) t sw in the 2mhz oscillation mode* 3 v dd =1.8 to 3.6v 0.4 D D s sclk output pulse width (master mode) t sw D sclk* 1 0.4 sclk* 1 0.5 sclk* 1 0.6 s in the 500khz oscillation mode* 2 output load 10pf D D 500 sout output delay time (slave mode) t sd in the 2mhz oscillation mode* 3 output load 10pf D D 240 ns in the 500khz oscillation mode* 2 output load 10pf D D 500 sout output delay time (master mode) t sd in the 2mhz oscillation mode* 3 output load 10pf, v dd =1.8 to 3.6v D D 240 ns sin input setup time (slave mode) t ss D 80 D D ns in the 500khz oscillation mode* 2 500 D D sin input setup time (master mode) t ss in the 2mhz oscillation mode* 3 v dd =1.8 to 3.6v 240 D D ns in the 500khz oscillation mode* 2 300 D D sin input hold time t sh in the 2mhz oscillation mode* 3 v dd =1.8 to 3.6v 80 D D ns * 1 : clock cycle selected with snck2?0 of the serial port n mode register (sionmod1) (n= 0, 1) * 2 : when 500khz oscillation is selected with oscm2 of the frequency control register 0 (fcon0) * 3 : when 2mhz oscillation is selected with oscm2 of the frequency control register 0 (fcon0) t sd sclkn* sinn* soutn* *: indicates the tertiary function of the port (n= 0,1) t sd t ss t sh t sw t sw t scyc
fedl610406-05 ML610404/ml610405/ml610406 27/30 ac characteristics (rc oscillation a/d converter) condition for v dd =1.8 to 3.6v (v dd =1.8 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation resistor rs0,rs1,rt0, rt0-1,rt1 cs0, ct0, cs1 740pf 1 D D k ? f osc1 resistor for oscillation=1k ? 457.3 525.2 575.1 khz f osc2 resistor for oscillation=10k ? 53.48 58.18 62.43 khz oscillation frequency v dd = 3.0v f osc3 resistor for oscillation=100k ? 5.43 5.89 6.32 khz kf1 rt0, rt0-1, rt1=1k ? 7.972 9.028 9.782 ? kf2 rt0, rt0-1, rt1=10k ? 0.981 1 1.019 ? rs to rt oscillation frequency ratio *1 v dd = 3.0v kf3 rt0, rt0-1, rt1=100k ? 0.099 0.101 0.104 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt0-cs0 oscillation) f oscx (rt0-1-cs0 oscillation) f oscx (rt1-cs1 oscillation) kfx = f oscx (rs0-cs0 oscillation) , f oscx (rs0-cs0 oscillation) , f oscx (rs1-cs1 oscillation) ( x = 1, 2, 3 ) v dd v ddl c l v ss c v rt0, rt0-1, rt1: 1k ? /10k ? /100k ? rs0, rs1: 10k ? cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf rcm frequency measurement (f oscx ) input pin vih vil *1: input logic circuit to determine the specified measuring conditions. cs0 rt0 in1 cs1 rs1 rt1 cs0 rs0 rs0 rct0 rt0-1 ct0 rt0 cs1 rs1 rt1 in0 cvr0 cvr1 (note 1)
fedl610406-05 ML610404/ml610405/ml610406 28/30 condition for v dd =1.25 to 3.6v (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation resistor rs0,rs1,rt0, rt0-1,rt1 cs0, ct0, cs1 740pf 1 D D k ? f osc1 resistor for oscillation=6k ? 81.93 93.16 101.2 khz f osc2 resistor for oscillation=15k ? 35.32 38.75 41.48 khz oscillation frequency v dd = 1.5v f osc3 resistor for oscillation=105k ? 5.22 5.65 6.03 khz kf1 rt0, rt0-1, rt1=1k ? 2.139 2.381 2.632 ? kf2 rt0, rt0-1, rt1=10k ? 0.973 1 1.028 ? rs to rt oscillation frequency ratio *1 v dd = 1.5v kf3 rt0, rt0-1, rt1=100k ? 0.142 0.147 0.152 ? f osc1 resistor for oscillation=6k ? 85.28 94.58 103.3 khz f osc2 resistor for oscillation=15k ? 35.72 38.87 41.78 khz oscillation frequency v dd = 3.0v f osc3 resistor for oscillation=105k ? 5.189 5.622 6.012 khz kf1 rt0, rt0-1, rt1=1k ? 2.227 2.432 2.626 ? kf2 rt0, rt0-1, rt1=10k ? 0.982 1 1.018 ? rs to rt oscillation frequency ratio *1 v dd = 3.0v kf3 rt0, rt0-1, rt1=100k ? 0.141 0.145 0.149 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt0-cs0 oscillation) f oscx (rt0-1-cs0 oscillation) f oscx (rt1-cs1 oscillation) kfx = f oscx (rs0-cs0 oscillation) , f oscx (rs0-cs0 oscillation) , f oscx (rs1-cs1 oscillation) ( x = 1, 2, 3 ) note: ?please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and in0/in1 pin), including cvr0/cvr1. especially, do not have long wiring between in0/in1 and rs0/rs1. the coupling capacitance on the wir es may occur incorrect a/d conversion. also, please do not have signals which may be a source of noise around the node. ?when rt0/rt1 (thermistor and etc.) requires long wiring due to the restricted placement, please have v ss (gnd) trace next to the signal. ?please make wiring to components (capacitor, resistor, and so on) n ecessary for objective measurement. wiring to reserved components may affect to the a/d conversion operation by noise the components itself may have. rt0, rt0-1, rt1: 1k /10k /100k ra0, ra0-1, ra1: 5k rs0, rs1: 15k cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf frequency measurement (f oscx ) input pin *1: input logic circuit to determine the specified measuring conditions. (note 1) v dd v ddl c l v ss c v rcm vih vil cs0 rt0 in1 cs1 rs1 rt1 cs0 rs0 rs0 rct0 rt0-1 ct0 rt0 cs1 rs1 in0 cvr0 cvr1 ra1 ra0-1 rt1 ra0
fedl610406-05 ML610404/ml610405/ml610406 29/30 revision history page document no. date previous edition current edition description fedl610406-01 dec.15,2011 ? ? final edition fedl610406-02 dec.5,2012 15 15 remove the word ?appendixc? in the table. 17 17 correct the symbol of capacitor at v ddl. 19 19 the notes about c v , c l were added. 19,25 19,25 the value of capacitor cl was changed to 2.2uf. fedl610406-03 feb.21,2014 all all change header and footer 3 4 change from "shipment" to " product name ? supported function " 20 18 correct minimum time of power-on reset generated power rise time 3,5,6,7, 31 4 delete package products fedl610406-04 apr.18,2014 4 4 correct the ?product name ? supported function? - 17 add clock generation circuit operating conditions 18 18 change "reset" to " reset pulse width (p rst )" and " power-on reset activation power rise time (t por )". 18 18 correct minimum time of power-on reset generated power rise time fedl610406-05 may.23,2014 18 18 correct the c gl ?s value and the c dl ?s value of dc characteristics (1/5)?s note no.2
fedl610406-05 ML610404/ml610405/ml610406 30/30 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants and any othe r information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accord ance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of h uman injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controlle r or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2011-2014 lapis semiconductor co., ltd.

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